1. Field of the Invention
The present invention relates to a method for fabricating a semiconductor device and a semiconductor device fabricated by the method, and more particularly, to a method for fabricating a BiCDMOS device where a bipolar junction transistor, a complementary metal-oxide-semiconductor (CMOS) electric field effect transistor and a double diffused metal-oxide-semiconductor (DMOS) electric field effect transistor are formed on a single wafer, and to a BiCDMOS device fabricated by the method.
2. Description of the Related Art
BiCDMOS technology includes bipolar technology, CMOS technology and DMOS technology. That is, BiCDMOS technology can attain low power consumption, a small noise margin and a high integration density for CMOS technology, high switching speed and input and output speed for bipolar technology, and high power characteristics for DMOS technology. Thus, a power device and a logic device can be integrated onto a single chip, thereby reducing the chip size, reducing power consumption and withstanding high voltage and drive at high current. However, the technology of fabricating a BiCDMOS device is very complicated and requires many mask layers, thereby increasing manufacturing cost. Thus, a method for fabricating a BiCDMOS device reducing the number of required mask layers to lower the unit cost and increase performance of the device is required.
Meanwhile, a DMOS device included in the BiCDMOS device exhibit problems such as turn-on phenomenon of a parasitic transistor, and device failure due to excessive reverse-directional current.
FIG. 1 is a sectional view showing an example of a horizontal DMOS transistor included in a conventional BiCDMOS device, showing two cells in common using a source electrode.
Referring to FIG. 1, an n-type highly-doped buried layer 11 is formed on a semiconductor substrate 10 doped with p-type impurities, and an n-type lightly-doped epitaxial layer 12 is formed on the n.sup.+ -type buried layer 11. An n-type lightly-doped well region 13 is formed on the n-type epitaxial layer 12, and a p-type base region 14 is formed on the n-type well region 13. Also, n-type base regions 15a and 15b are formed at the sides of the p-type base region 14, spaced apart by a predetermined distance. N-type highly-doped source regions 16a and 16b are formed in the p-type base region 14. Meanwhile, n-type highly-doped drain regions 17a and 17b are formed on the n-type base regions 15a and 15b, respectively.
A source electrode 18 is formed to electrically contact the n-type source regions 16a and 16b and the p-type base region 14. Gate electrodes 19a and 19b are formed at the sides of the source electrode 18, spaced apart from the source electrode 18 by a predetermined distance. The gate electrodes 19a and 19b are formed on an oxide layer 20 at the sides of the n-type source regions 16a and 16b and over the p-type base region 14. Also, drain electrodes 21a and 21b electrically contact the n-type drain regions 17a and 17b. Meanwhile, the source electrode 18, the gate electrodes 19a and 19b and the drain electrodes 21a and 21b are insulated by an insulating layer 22.
In the horizontal DMOS transistor, a parasitic npn bipolar transistor composed of the n-type source regions 16a and 16b, the p-type base region 14 and the n-type drain regions 17a and 17b is turned on by voltage drop due to a current flowing through resistance R.sub.b of the p-type base region 14. Consequently, the gate electrodes 19a and 19b cannot be controlled, and as such, a device can be damaged. The current flowing through the resistance R.sub.b of the p-type base region 14 includes first zener diode current I.sub.z1. Here, the first zener diode current I.sub.z1 means current flowing through a first zener diode component 24a when overcurrent flows due to the inductance component of a load during the turn-off of a device to apply a voltage more than a predetermined voltage (zener voltage) between the p-type base region 14 and the drain regions 17a and 17b.
A deep p+ region 23 is formed deeply in the p-type base region 14. The deep p+ region 23 reduces resistance R.sub.b of the p-type base region 14. In addition, a second zener diode current I.sub.z2 flowing through a second zener diode component 24b is formed between the deep p+ region 23 and the n-type buried layer 11, thereby reducing the amount of first zener diode current I.sub.z1 that passes through the resistance R.sub.b of the p-type base region 14.
However, an additional mask layer is required for forming the deep p+ region 23, which complicates the fabrication process. Also, in a low pressure process, even though the concentration of the p+ region 23 is increased, the zener voltage of the first zener diode component 24a may be lower than the zener voltage of the second zener diode component 24b. Thus, even though the resistance R.sub.b of the p-type base region 14 is reduced, the first zener diode current I.sub.z1 flows through the resistance R.sub.b pf the p-type base region 14, such that the parasitic npn bipolar transistor can be easily turned on. As a result, the reliability of the device can be deteriorated.